library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity instr_reg is
generic ( 	numBit	: integer := 8;
		opSize	: integer := 4);
port ( 	clock	: in   std_logic;
		reset	: in   std_logic;
		enable	: in   std_logic;
		data_in 	: in   std_logic_vector (numBit-1 downto 0);
		opcode 	: out std_logic_vector (opSize-1 downto 0);
		r_s 		: out std_logic;
		r_t 		: out std_logic;
		r_d 		: out std_logic_vector (1 downto 0);
		Imm		: out std_logic_vector (3 downto 0)
	);
end instr_reg;

architecture Behavioral of instr_reg is
signal ireg 	: std_logic_vector(numBit-1 downto 0);
signal opc_tmp	: std_logic_vector(opSize-1 downto 0);
begin
	
	REG: entity work.ffdcN(structural) generic map(numBit)
	port map (clock,reset,enable,data_in,ireg);

	opc_tmp		<= ireg (7 downto 4);
	r_s 			<= ireg (3);--TODO: here the registers should be on two bits
	r_t 			<= ireg (2);
	r_d 			<= ireg (1 downto 0) when opc_tmp(3) = '1' else "0" & ireg (2);
	Imm 		<= ireg (3 downto 0) when opc_tmp = "0111" else "00" & ireg (1 downto 0);
	
	opcode		<= opc_tmp;

end Behavioral;
